without decompression. Share on. Equivalence Checking Using Cuts and Heaps Andreas Kuehlmann Florian Krohm IBM Thomas J. Watson Research Center Presented by: Zhenghua Qi Previous approaches—BDD Equivalence checking in combinational verification BDD based approaches The functions of the two circuits to be compared are converted into canonical forms which are then structurally compared. The most commonly used methods to do formal verification of circuits use binary decision diagrams (BDD) [2] and its derivatives, namely ordered BDD (OBDD), ordered functional decision diagrams (OFDD), In computer science, a binary decision diagram (BDD) or branching program is a data structure that is used to represent a Boolean function.On a more abstract level, BDDs can be considered as a compressed representation of sets or relations.Unlike other compressed representations, operations are performed directly on the compressed representation, i.e. 1. For details on the efficient implementation of BDD pack-ages see [1, 9, 12]. using BDD and SAT methods. Equivalence checking using cuts and heaps. A number of recently proposed BDD based approaches have met with considerable success in this area. There are basically two problems in the verification of designs: model checking and equivalence checking. The most commonly used methods to do formal veri cation of circuits use binary de-cision diagrams (BDD) [2] and its derivatives, namely or-dered BDD (OBDD), ordered functional decision diagrams (OFDD), multi terminal BDD (MTBDD), binary moment Introduction The problem of checking the equivalence of combina-tional circuits is of key significance in the verification of digital circuits, and has been the subject of significant con-tributions in recent years. As a result, several approaches have been proposed for solving theCombinational Equiv- Most of the work on equivalence checking is done in the domain of formal veri cation. If there exists a design bug, formal verification techniques produce a counter-example to support debugging processes. Circuit Equivalence Checking Checking the equivalence of a pair of circuits − For all possible input vectors (2#input bits), the outputs of the two circuits must be equivalent − Testing all possible input-output pairs is CoNP- Hard − However, the equivalence check of circuits with “similar” structure is easy [1] − So, we must be able to identify shared 110-125, 1995. compared with pure BDD-based approaches. ... "Exploiting structural similarities in a BDD-based verification method," in Proceedings of the Znd International Conference on Theorem Provers in Circuit Design, pp. Formal verification is equivalent to simulating all the cases in logic simulation. On the contrary, for Combinational Equiv- Abstract: This paper addresses the problem of combinational equivalence checking (CEC) which forms one of the key components of the current verification methodology for digital systems. Most BDD packages allow for many types of syn-thesis operations such as AND and OR; however, vari-able substitution and quantification operations which are used extensively in sequential equivalence checking are also included. Authors: Andreas Kuehlmann. Most of the work on equivalence checking is done in the domain of formal verification.

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